In integrated circuit device (“IC”) manufacture, a succession of material layering processes takes place in which metal, dielectric, and semiconductor materials are successively applied to the surface of the wafer, typically by deposition. A typical sequence is to start with a substrate; then form active devices in one or more semiconductor and dielectric layers; and then form metal interconnects to connect the different layers of the integrated circuit device together. The interconnects are vias and trenches, formed by photolithographically patterning a dielectric surface followed by etching and planarizing. Many stacked layers of the IC are thus electrically interconnected.
As each successive layer is completed, its upper surface must be finished to a high degree of planarity with respect to other already-fabricated metal and dielectric surfaces throughout the wafer. So, for example, in the above process, following a metallization excess metal is removed. The resulting ideally planar surface must be as parallel as possible to the most recently planarized surface.
The process used for planarization in most semiconductor wafer fabrication is chemical mechanical planarization (CMP). CMP involves pressing a semiconductor wafer against a moving polishing surface wetted with a chemically reactive, abrasive slurry in a manner disclosed, for example, in U.S. Pat. No. 5,423,716. A problem with CMP is that at places along a polished surface, the CMP mechanism has a tendency to create uneven, non-planar portions. These take several forms, the most recognized of which is dishing and erosion. The term “planarization” sometimes is used to refer to processes for minimizing dishing and erosion topographies. Both dishing and erosion can lead to more resistive interconnects and cause problems at subsequent CMP and photolithography steps due to the resulting lack of planarity.
Accordingly, for some time now, much work has been directed at reducing the extent of dishing and erosion. At the same time, as integrated circuit fabrication methods have created ever smaller geometries, the planarity requirements for a number of critical process steps have become increasingly stringent. For example, the most critical step for photolithography is typically the polysilicon gate patterning step, which is directly impacted by the topography of the underlying isolation layer. Lack of planarity at this stage is often fatal to the wafer, as the following illustrates.
The most advanced semiconductor processes currently in production typically use a Shallow Trench Isolation (STI) scheme to separate active device regions on the silicon substrate. STI has supplanted the older localized oxidation of silicon (LOCOS) isolation method because it allows for smaller geometries due to the absence of an encroaching “bird's beak” inherent in the LOCOS method. For geometries smaller than 0.35 microns, STI is the preferred isolation method.
The STI process begins with a bare silicon wafer, possibly already patterned with photolithography alignment marks. The wafer is typically oxidized to form a thin “pad oxide” layer which is used as an aid to relieving surface stress. On top of the pad oxide is deposited a silicon nitride film around 1000 to 2000 A thick. Next, photoresist is applied and the trench pattern is exposed and developed in the photoresist. An etch process is used to etch through the nitride and pad oxide and into the underlying silicon, typically to a depth of 3000-6000 A. These trenches' delineate the silicon which will form transistors and other components on the wafer surface, and when filled with oxide will insulate (isolate) these devices from one another.
Following trench etch, the remaining photoresist is stripped off, and oxide is deposited on the wafer to fill the trenches. Various different combinations of thermal, silane, LPCVD, HDP or other types of oxide may be used at this stage. Frequently a small amount of high quality oxide (i.e. thermal or silane) is grown first in the trench to serve as a “liner”, followed by a deposition of a larger amount of lower quality oxide (LPCVD, HDP) to completely fill the trenches with some additional amount of oxide overfill.
At this point, a cross-section of a portion of the wafer surface typically is as shown schematically in FIG. 1. The trenches have been filled with oxide, but the oxide has also been deposited on top of the active regions. The oxide over the active regions needs to be removed in order to continue processing, and this task is normally accomplished with CMP. An ideal post-CMP cross-section is depicted in FIG. 2.
The goal of the CMP process is to remove all the oxide over the active regions, while avoiding polishing through the nitride or excessively dishing into the trench oxide. The nitride is stripped off after the CMP process is completed, using a hot phosphoric acid bath; but the nitride cannot be removed if there is any oxide remaining on top of it. Residual nitride of this type will render the chip nonfunctional. On the other end of the spectrum, if the nitride is completely polished away anywhere on the wafer, the active silicon will be exposed to the CMP process and become contaminated, again resulting in a nonfunctional chip. An example of a cross-section of what a poorly planarized chip might look like is shown in FIG. 3. At the left and right edges areas are seen where there is residual oxide over nitride. These areas will result in residual nitride and render the device unusable. Further, the oxide to active step varies, which is also not desirable.
The above illustration describes the bare minimum requirements for a CMP process at STI. However, as topography requirements become more stringent, the best current CMP performance is increasingly inadequate. In an ideal case the step height from the top of the active region to the top of the trench oxide (post-nitride strip) would be the same everywhere in the current die; and on every die in the wafer—regardless of local pattern density, feature size, or die location. In addition, this step height would be targeted such that, by the time the wafer was processed up to poly gate patterning, the top of the trench oxide would be coplanar with the top of the active region. Even for the bare minimum scenario, traditional CMP processes have not been sufficient to achieve consistently good results without further process accommodations.
Specifically, the first generation of STI processes generally addressed the issue of inadequate planarization by using a “reverse active mask etchback” technique. Here, the wafer is masked post-oxide fill using a pattern that is the inverse of the original trench mask. This is either achieved by using the same mask as was used at trench patterning but using a negative-tone resist; or by using the same resist but exposing a second mask which is the photographic negative of the trench mask. The result is that the developed mask covers the trenches while leaving the active regions open, as shown in FIG. 4. Then a wet or dry etch process is used to remove most or all of the oxide over the active regions. The result of using an anisotropic dry etch is shown in FIG. 5 which depicts post-resist strip. After the etch and mask-strip steps, the wafer is polished. This approach causes the wafer incoming to CMP to have much less topography; and therefore CMP has to remove less material and the wafer post-CMP is well planarized. The downside to this method is that it adds several process steps, including a very expensive photolithography step. Since the trench/active layer has some of the smallest geometries on the chip, the photo stepper used to expose this layer will be one of the most advanced and therefore most expensive tools. Since the reverse active masking step uses the exact same geometries as the active masking step, this also requires using the most expensive stepper and therefore is cost prohibitive.
In an effort to eliminate the reverse active mask process, dummy tiles were introduced at the STI level in order to facilitate “direct polishing” of STI. These dummy tiles are small, repeating active features added to large trench areas to increase the effective pattern density in these large trenches. The manner in which they have been added, is established by “rules”. Tile size and placement is controlled by the same set physical dimensions in all parts of the die area. The added tiles have no electrical or device function, but exist solely for topographic reasons. By adding tile features, the lowest areas in the die (wide trench areas, such as in the scribe lines) are raised up to be closer in pattern density to the functional areas of the die. This helps to reduce the topography variation within the die pre-CMP by making the amount of oxide distribution more uniform in all areas of the die. Combined with a well-executed CMP process, rule-based tile placement allows one to generate functioning STI-based chips more economically than the reverse active mask procedure. Although the resulting post-CMP topography will usually be worse than when using the reverse active mask, the rule-based placement topography is good enough and the cost savings involved justifies the compromise.
An example of the use of rule-based polishing dummy tiles in a semiconductor device layer is found in U.S. Pat. No. 5,885,856.
Alternatively, instead of simply filling all available open spaces with a repeating rule-based dummy tile pattern, tiles may be designated for placement more deliberately, where they will provide an added benefit to the final post-CMP topography. This approach is known as “model-based placement” A variety of model-based tile placement algorithms have been developed, each seeking to strike an optimum balance among the factors of tile size, tile proximity to circuit features, tile density, and polish uniformity. Model-based tiling methods of placing the tiles, require that the CMP process be characterized thoroughly as to, for example, pad bending, dishing, erosion and polish rate; and then modeled by a set of equations. These equations are then used by a computer algorithm to determine placement for dummy features in the available open spaces so that they will minimize the post-CMP topography. U.S. Pat. No. 6,369,158 exemplifies model-based tile placement in its use of a step in which the specific CMP process influences tile placement.
Either rule-based or model-based tile placement of dummy tiles provides a means to achieve a tighter spatial distribution of active density which generally improves CMP results by reducing non-uniformities. However, in both of these approaches, the size of the tile and the method of placement impact the length scale at which the distribution improvement is achieved.
Rule-based tiling systems have been successful at improving short-scale (i.e., in the range of from 3 um to 30 um) tile non-uniformity, by filling all available open space with small repeating tile patterns. The resulting die, while more uniform at the tile feature scale in this range sometimes have unacceptable die-scale topography variation.
Model-based tiling has been used to address die-scale (i.e., in the range of from 1,000 um to 30,000 um) topography by placing large tiles in the appropriate areas of the die based on the prediction of a topography model. These schemes typically use “single length scale” approaches, as exemplified in U.S. Pat. Nos. 6,093,631 and U.S. Pat. No. 6,323,113. But the resulting model-tiled die, while having good die-scale topography, showed high topography variation at the feature scale of from 3 um to 30 um. Experience has shown that each tiling scheme can affect a particular scale regime. Increasingly, however, the need is to address both long and short scale concerns; and in so doing, to simultaneously address different sources of variation having to do with oxide vs. nitride densities.